Date of Award




Document Type


Degree Name

Doctor of Philosophy (PhD)


Department of Nanoscale Science and Engineering


Nanoscale Engineering

Content Description

1 online resource (xvii, 166 pages) : illustrations (some color)

Dissertation/Thesis Chair

Alain C Diebold

Committee Members

James R Lloyd, Michael Liehr, Andy C Rudack, Sitaram Arkalgud


Bottom-up and conformal, Finite element modeling, stress-assisted, Through silicon via (TSV), void growth, X-ray microscopy, Three-dimensional integrated circuits, Interconnects (Integrated circuit technology), Finite element method, Stress corrosion

Subject Categories

Engineering | Materials Science and Engineering | Nanoscience and Nanotechnology


Fabricating through-silicon vias (TSVs) is challenging, especially for conformally filled TSVs, often hampered by the seam line and void inside the TSVs. Stress-assisted void growth in TSVs has been studied by finite element stress modeling and X-ray computed tomography (XCT). Because X-ray imaging does not require TSVs to be physically cross-sectioned, the same TSV can be imaged before and after annealing. Using 8 keV laboratory-based XCT, voids formed during copper electroplating are observed in as-deposited samples and void growth is observed at the void location after annealing. We hypothesize that the mechanism generating voids is hydrostatic stress-assisted void growth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods. The peaks of the hydrostatic stress and its gradient are shown to be around the edge of the void. Comparing simulated results and experimental data shows that void growth in TSVs is stress-assisted: vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.