Date of Award

Spring 2026

Language

English

Embargo Period

4-20-2026

Document Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

College/School/Department

Department of Nanoscale Science and Engineering

Program

Nanoscale Engineering

First Advisor

Christophe Vallée

Committee Members

Christophe Vallée, Nathaniel Cady, Carl Ventrice, Subhadeep Kal, Eric Liu

Keywords

TaN, SiOCH, etching, plasma, BEOL, dielectric

Subject Categories

Electronic Devices and Semiconductor Manufacturing | Nanotechnology Fabrication | Semiconductor and Optical Materials | VLSI and Circuits, Embedded and Hardware Systems

Abstract

Transistor scaling has continued according to Moore’s Law for over fifty years. As transistor size decreases, adequate power delivery is required to enable transistor scaling without performance loss. Power delivery is provided by a metal interconnect network with insulating dielectric that connects the transistor level to the power source, the signal speed within this metal line network limiting transistor level switching speeds. Reduction of signal delay has moved from primarily dimension-based improvement towards adoption of conductor and dielectric materials with lower resistivity and a reduced dielectric constant value, respectively: transitioning from Al/SiO2 to Cu/low-κ SiOCH. With this transition comes new integration in the form of the dual damascene flow, two key points of change being the adoption of a diffusion barrier, commonly a TaN/Ta bilayer, and the need for chemical mechanical planarization for both the diffusion barrier and Cu overfill removal. Low-κ SiOCH is mechanically unstable and can be damaged by the chemical mechanical planarization process, this damage propagating through the metal interconnect network and degrading device performance. It is proposed to mitigate low-κ SiOCH loss by eliminating contact between the chemical mechanical planarization process and the dielectric, using TaN as the etch stop. TaN will then be removed by a selective, radical-based, plasma etching process.

This dissertation accomplishes the development and investigation of several iterations of a radical based TaN plasma etch process selective with respect to low-κ SiOCH and electrically validates these results on a fabricated metal-insulator-semiconductor capacitor test vehicle. The plasma processes developed extend current knowledge regarding prevention of low-κ SiOCH damage when using F-based plasmas and this work introduces new techniques to quantify and remove damaged layers produced. It is first shown that by addition of an SiOx coating to a plasma chamber wall before processing, one can reverse SiOCH to TaN etch selectivity with a radical dominated NF3/Ar discharge, accomplishing selective removal of TaN compared to SiOCH when a chamber coating is applied. The chamber wall coating is found to act as a solid precursor for addition of atomic oxygen species that serve to enable sufficient SiOxFy deposition, selectively on the SiOCH surface. Moving from a solid precursor to direct injection, it is determined that a SiF4/O2 discharge can accomplish the same selective deposition regime as was demonstrated with a chamber wall coating, allowing a more controllable removal of TaN with selectivity to SiOCH. However, before SiOxFy deposition occurs, C extraction from the SiOCH itself occurs before deposition effectively blocks SiOCH damage. To reduce damage, cryogenic temperatures are explored and O2 is removed from the plasma discharge. It is found that by tuning temperature, one can reverse SiOCH to TaN etch selectivity, once again, to enable selective etching of TaN with respect to SiOCH with an NF3/SiF4 discharge free of injected O2. Some damage is still apparent on the SiOCH surface, mainly manifesting as C depletion, but by introduction of a HF/NH3 process after NF3/SiF4 processing, this SiOCH damage layer can be selectively removed from the SiOCH bulk, with complete restoration of the SiOCH C signal observed by X-ray photoelectron spectroscopy. Additionally, the damaged layer thickness was quantified by the inherent selectivity of the HF/NH3 process to SiOCH bulk, the etch amount of NF3/SiF4 processed SiOCH being equivalent to the damaged layer thickness. Through increase of SiF4 flow during the NF3/SiF4 process, the damaged layer thickness was decreased by ~25 %. The combined NF3/SiF4 process and HF/NH3 removal of the damaged layer was electrically validated to show similar device defect density as that of a test device with pristine SiOCH of the same thickness.

License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

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