ORCID
https://orcid.org/0009-0007-9126-8721
Date of Award
Spring 2025
Language
English
Embargo Period
4-1-2025
Document Type
Dissertation
Degree Name
Doctor of Philosophy (PhD)
College/School/Department
Department of Nanoscale Science and Engineering
Program
Nanoscale Engineering
First Advisor
Woongje Sung
Committee Members
Woongje Sung, Unnikrishnan Pillai, Harry Efstathiadis, Bongmook Lee, Nadeemullah Mahadik
Keywords
4H-SiC, Power Devices, Device Architecture, Room Temperature Ion Implantation, JBSFETs, BiDFETs
Subject Categories
Nanoscience and Nanotechnology
Abstract
The work presented in this document focuses on advancing the overall design, performance, and reliability of 4H-SiC power devices through various design architectures and processing strategies. Power devices serve as an efficient way to control the flow of power and thus are utilized throughout a vast number of different systems. These systems accommodate various current and voltage ratings to support applications such as personal electronics, electric vehicle components, fast chargers, renewable energy solutions, and energy storage systems. As the demand for these applications grows alongside global electrification and sustainability efforts, minimizing power losses becomes increasingly important. Therefore, developing efficient and cost-effective power devices is crucial for achieving global electrification and sustainability goals.
Similar to most of the semiconductor industry, Silicon-based power devices have dominated the market across a wide range of voltage applications due to the material's well-established device design and fabrication process. However, the demand for more efficient power devices, particularly for voltage ratings exceeding 600V, has driven interest in wide bandgap materials such as 4H-SiC, which offer superior material properties compared to Silicon. These superior properties enable the design of thinner and more heavily doped epitaxial drift layer to support a given breakdown voltage, leading to a significant reduction in the on-resistance of 4H-SiC devices compared to Silicon-based ones at voltage ratings greater than 600V. However, the drift region is not the only critical component of these power devices. Other regions, such as the edge termination and active area, must also be optimized to ensure efficient and reliable performance while keeping manufacturing costs in mind. To achieve this, three main areas are being investigated: the implementation of full-scale Room Temperature (RT) ion implantation for 4H-SiC devices, the further development of the Junction Barrier Schottky Diode Integrated MOSFET (JBSFET), and the continued advancement of the Monolithically Integrated Bi-Directional Field Effect Transistor (BiDFET).
In 4H-SiC device fabrication, ion implantation was traditionally performed at elevated temperatures to mitigate lattice damage and prevent the generation of Basal Plane Dislocations (BPDs). However, these high-temperature ion implantation processes present several challenges for large-scale manufacturing, making the adoption of a RT ion implantation a more desirable process if significant BPD generation can be avoided. As a result, this dissertation presents a detailed investigation into the full-scale RT ion implantation process for 4H-SiC power devices. The study not only examines the implantation dose, which has been explored in previous research, but also considers the implantation profile and the overall architecture for 4H-SiC power devices.
4H-SiC MOSFETs have traditionally been paired with Junction Barrier Schottky (JBS) diodes to bypass the built-in body diode and enable unipolar current conduction during third-quadrant operation. However, this co-package solution adds additional complexities as more device components are needed, and thus it is crucial to address this to further the adoption of 4H-SiC power devices. As a result, the JBS diode was integrated into the MOSFET structure thereby creating a single device solution in the form of the JBS diode integrated MOSFET (JBSFET), greatly improving power device performance and area efficiency. This dissertation presents further development of the JBSFET, including advancements in second-generation designs and the exploration of various device architectures to support the development of third-generation JBSFETs.
As global electrification efforts progress, the demand for efficient Bi-Directional switches capable of conducting current and blocking voltage in both the forward and reverse directions also grows. Due to the material properties and processing advancement in 4H-SiC, novel designs such as the monolithically integrated BiDFET have been developed. Although this approach simplifies the design of Bi-Directional switches, it has not yet been demonstrated at medium voltage ratings, which are crucial for renewable energy and grid-tied energy storage applications. As a result, this dissertation presents the further development of a medium-voltage monolithically integrated BiDFET, as well as a novel edge termination technique to reduce the required wafer area required for monolithic Bi-Directional switch integration.
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Recommended Citation
Mancini, Stephen A., "Advancing 4H-Silicon Carbide Power Device Technology through Improved Device Design, Performance and Reliability" (2025). Electronic Theses & Dissertations (2024 - present). 128.
https://scholarsarchive.library.albany.edu/etd/128
